|
Min |
Typical |
Max |
| Supply voltage (Vdc) |
4.75 |
5 |
5.25 |
| Power consumption (W) |
0.8 |
|
2 |
| Input sensitivity data & clock voltage (Vpp) |
0.3 |
0.8 |
1 |
| Normalized back face voltage (mV) |
|
500 |
|
| Monitor bias voltage slope (MV/mA) |
20 |
| Laser Degrade Alarm |
|
|
|
| 6-1, Activated (pin 8) (Vdc): |
0 |
|
0.2 |
| 6-2, Deactivated (Vdc): |
2.4 |
|
5.0 |
| LDA - Activation Delay (ms) |
|
200 |
|
| LDA - Deactivation Delay (ms) |
|
400 |
|
| Shut Down Command - Enable Laser (Vdc) |
0 |
|
0.8 |
| Shut Down Command - Disable Laser (Vdc) |
2.0 |
|
5.0 |
| Response Time to Disable Laser (ms) |
|
500 |
|
| Response time to Enable Laser (ms) |
|
500 |
|
| Electrical Return Loss: |
| Clock 1MHz - 2.2GHz (dB): |
|
9 |
|
| Clock 2.2GHz - 2.8GHz (dB): |
|
13 |
|
| Data 1MHz-1.5GHz (dB): |
|
13 |
|
| Data 1.5MHz-2.5GHz (dB): |
|
9 |
|
| Clock and Data differential skew (ps): |
|
40 |
|
| Clock and Data differential voltage |
|
|
|
| Per complimentary rail (AC coupled into 50 ohm) (Vpp): |
0.3 |
|
1.0 |
| Per complimentary rail (Vpp): |
0.15 |
|
0.5 |
| Clock and Data rise time (20% - 80%) (ps): |
|
150 |
|
| Clock and Data fall time (80% - 20%) (ps): |
|
150 |
|
| Data Format: |
(Scrambled NRZ) |
| Clock Duty Cycle (%): |
40 |
50 |
60 |
| Consecutive Identical Bits: |
CID 72 bits |
| Logic level5: |
TTL compatible |